1. Field of the Invention
The present invention relates to an image synthesis apparatus for synthesizing images using texture mapping, and in particular to an image synthesis apparatus for realizing high-speed image synthesis with an inexpensive, simple structure having a small memory capacity by way of a memory structure for storing data required for image synthesis.
2. Description of the Related Art
Texture mapping is one of the known methods of so-called three-dimensional computer graphics (CG) for synthesizing a two-dimensional image from a three-dimensional structure of an object using a computer.
By texture mapping, a natural-looking image can be synthesized because pixel values of synthesized image data are obtained based on pixel values of the original image data. However, a large amount of calculation and the large memory access necessary for image synthesis performed by texture mapping often require use of an image synthesis apparatus including a plurality of processors.
Briefly referring to FIG. 10, a conventional image synthesis apparatus including a plurality of processors will be described. FIG. 10 is a block diagram of a conventional image synthesis apparatus.
As is illustrated in FIG. 10, a plurality of processors 100a, 100b, . . . (hereinafter, indicated as 100 collectively) are respectively connected to local memories 102a, 102b, . . . (hereinafter, indicated as 102 collectively) and also to frame memories 103a, 103b, . . . (hereinafter, indicated as 103 collectively) through buses 101a, 101b, . . . (hereinafter, indicated as 101 collectively). The frame memories 103 are all connected to an image bus 104.
In the conventional image synthesis apparatus, the total work load is divided into the plurality of processors 100, and each processor synthesizes an image of one of the areas of an object allocated thereto. In detail, each processor 100 stores original image data and image drawing data required for image synthesis to the corresponding local memory 102 and processes such data to generate synthesized image data of the area allocated thereto. The synthesized image data generated by each processor 100 is stored in the corresponding frame memory 103. The frame memory 103 includes a memory such as a VRAM having two ports. Synthesized image data generated by each of the plurality of processors 100 are assembled by the image bus 104 and output.
Generally in such an image synthesis apparatus having a plurality of processors, the level of performance depends on how much the competition among the plurality of processors can be restricted to get the access to data shared by such processors. In the conventional image synthesis apparatus, the original image data and the image drawing data are stored in the local memories 102, and the synthesized image data of each area is stored in the corresponding frame memory 103. In this manner, deterioration in the performance caused by the competition to get the access to the data is avoided, and thus high-speed image synthesis is realized.
In the case when the synthesized image data which has already been generated by the processor 100 or the data which is being processed to generate the synthesized image data is used again as original image data in order to form an image including, for example, a transparent part or a part overlapped on another other part, one of the processors should access the synthesized image data generated by another processor. Since only a limited number of processors can access such data, such image synthesis cannot be performed at a high speed.
Further, in the conventional image synthesis apparatus, the plurality of local memories each need a memory area for the same original image data and the same image drawing data. This requires a large memory capacity and thus raises the cost of producing the apparatus.